Analysis of Full Adder Circuits
ABSTRACT:
In this paper, a comparison of various full adder circuits is analyzed. Full Adder circuits are extensively used in digital design. Different types of full adder such as Conventional CMOS, based on Ex-OR/Ex-NOR, Pass Transistor Logic(PTL), and Gate Diffusion Input (GDI)technique. From this, the GDI technique takes a fewer number of transistors and therefore consumes less power.
INTRODUCTION:
Now a day, a tremendous increase in the electronic industry is seen. The use of portable devices is also increasing. The evolution of nanotechnology has become a boon to electronic manufacturing. As the channel length reduces, the maximum number of transistors that can be embedded into a single chip increases. This gives rise to improved functionality. The current demands are high speed, low power, high throughput. So in VLSI, the circuits need good output with less power.
Full Adders are widely used in different combinational circuits, Application-Specific Integrated Circuits (ASICs). It is an essential component for the design and development of all types of processors like Digital Signal Processors (DSPs), Microprocessors, etc. It is the fundamental gate in many arithmetic circuits, such as adders and multipliers. Thus, upgrading the performance of the full adder block leads to the enhancement of overall system performance. To attain low power for large circuits, the basic component itself needs to be minimized in terms of power. Different low power techniques are available. The most widely used methods include PTL, which requires fewer transistors as compared with conventional CMOS circuits. The problem with this is improper output voltage swings due to the difficulty of PMOS to turn off. This even increases static power dissipation Other existing low power technique includes Hitachi CPL and DPL. Older low power technique includes Dynamic logic, Domino logic, NORA logic, Differential Cascode Voltage Switch(DCVS), MOS Current Mode Logic(MCML) and Clocked CMOS(C2CMOS). The latest low power circuits include the GDI technique which was introduced by A. Morgenshtein, A.Fish, and Israel Wagner in 2002[10]. This technique includes a unique cell library that can perform nearly eight different functions. Therefore, a large number of functions can be realized easily. Also as the number of transistors required is less and thus the power consumption is less.
Basic Full Adder:
A basic full adder circuit is used to add three one-bit binary numbers A, B, and C. It produces two one-bit outputs Sum and Carries out. The full Adder can be realized with a Boolean function such as:
Sum= ABC and Carry = AB + BC + AC
For an n-bit full adder carry in(C) is the carry out(carry) of the previous bit addition operation. Similarly, the carry-out is fed to another full adder as they carry in. Here the Sum operation is obtained by performing Ex-OR operation between three inputs, whereas the Carry output is obtained from AND and OR operations. It is observed in the equation.
Example: One-Bit Full-Adder:
The full-adder extends the concept of the half-adder by providing an additional carry-in (Cin) input, as shown in Figure 5.21. This is a design with three inputs (A, B, and Cin) and two outputs (Sum and Cout). This cell adds the three binary input numbers to produce sum and carry-out terms.
Any number of half-and full-adder cells can be connected to form an n-bit addition. Figure 5.23 shows the connections for a four-bit binary adder. In this design, there is no Cin input. Inputs A and B are four bits wide, and bit 0 (A(0) and B(0)) are the LSBs.
Various Existing Low Power Techniques For Full Adder Circuits
1. Conventional CMOS Circuit:
A basic CMOS circuit consists of PMOS and NMOS transistors arranged complementarily. PMOS transistors are present at pull up and NMOS transistors are complementarily arranged at the pull-down. The number of transistors is large since if n PMOS is present then NMOS are also present. The proper output swing is obtained. Since the number of transistors is large, therefore area gets increased and power consumption is also large. Fig.1 shows the circuit representation of a conventional CMOS-based full adder circuit. In this conventional circuit, to represent a one-bit full adder there requires 14T PMOS and 14T NMOS. The pull-up network consists of PMOS only and pull-down with NMOS only. This wide area circuit consumes high power
2. Based on Ez-OR/Ex-NOR and Transmission gate:
The Ex-OR/Ex-NOR gate is the basic building block of the adder, comparator, and parity generator/checker and encryption processor This method provides better swing and less propagation delay. A full adder is constructed with the Ex-OR/Ex-NOR circuit and four transmission gates[7]. The circuit is as shown in Fig. Proper output swing is obtained by connecting M1, M2, M3, and M4 transmission gates. The Sum operation is obtained by connecting M1 and M2 transistors whereas connecting M3 and M4 transistors to Ex-OR/Ex NOR outputs results in carrying out. The constructed full adder logic is represented in the following equations.
Sum=(AB)C+(AB)C and Carry = C(AB) + B(A + B)
The point p gives Ex-or output and q gives Ex-NOR output in Fig.2. For some operations, consider Ex-OR output is logic 1 then Ex-NOR output is logic 0, so M1 transmission gate turns ON and M2 transmission gate turns OFF. Therefore, the sum output of the circuit is the inverted input of C. Now Ex-OR output is logic 0 then Ex-NOR output is logic 1, M1 transmission gate turns OFF and M2 transmission gate turns ON. Therefore, the sum output of the circuit is the same as the input C. The circuit operation of the carry output is as follows. When Ex-OR output is logic 1 and Ex-NOR output is logic 0, the M3 transmission gate turns ON and the M4 transmission gate turns OFF. Therefore the carry output of the circuit is the same as that of C. When Ex-OR output is logic 0 and Ex-NOR output is logic 1, the M4 transmission gate turns ON and the M3 transmission gate turns OFF. Therefore, the carry output of the circuit is the same as input B[7]. This can be explained by the above equation (2). Here there are 20Tre needed overall so the total power consumption is large. But as compared to conventional CMOS 28T the power consumption is less.